My Story

Hi, there!

I am Chandrahaas Vadali, a first-year Ph.D student in the EECS department at UC Berkeley. My interests are in analog front-ends and mixed-signal circuit design for sensing hardware.

Industry

Before beginning my Ph.D., I worked at Intel for 3 years from 2021 in the Logic Technology Development division in Portland, OR. As a Device Engineer, I focused on improving the electrical performance of RibbonFETs and high-NA interconnects for process nodes beyond Intel 14A. My primary focus in FEOL was developing a robust low-k gate-spacer and facilitating healthy source/drain epitaxy for our Gate-All-Around FETs. On the backend, I worked on a novel area-selective deposition process aimed at improving the shorting margin between vias and adjacent metal layers.

Education

My training in Electrical Engineering and Materials Science has enabled me to work on hardware at different abstraction levels—from process development in the fab, to device physics and device modeling, to mixed-signal circuit design. I picked up my Bachelor’s degree from IIT Madras and Master’s from Stanford University.

Hobbies

I love running and biking! When I seek a peaceful escape, I go bikepacking, and you can read about my adventures in my blog. For the past four years, I’ve also been training in Carnatic music, a classical South Indian art form that emphasizes vocal performance.