Industry Experience

Intel Corporation

Device Engineer | Portland, OR | May 2021 - May 2024

I worked in the Device Engineering Group to enhance the performance of Intel’s future nodes using Gate-All-Around FETs (GAAFET) and Extreme-UV scaling. I received two Divisional Awards for my outstanding contributions to key performance and yield-improving projects in the early stages of process development.

My primary focus areas were –

Silicon Performance

Supported key FE process and module teams in the GAAFET loop by studying transistor low-voltage and short-channel behavior
Performed statistical analysis of device performance in controlled process change experiments, and develop physical models to explain the modulations
Driving novel backend projects to improve shorting margin, RC performance of interconnects
Developed and derived new metrics to study electrical performance on different kinds of test structures to study process improvements on BEOL

Test Chip Development

Supported Test Chip development by building transistors and isolation structures to test the limits of device physics and process margins
Designing leading-edge test vehicles on Cadence Virtuoso involves a detailed understanding of devices and process parameters

Skills: Electrical Characterization, Statistical Process Control, Device Physics, Thin Films, Physical Design

GlobalFoundries

Antenna Design and Electrical Modeling Intern | Albany, NY | June 2020 - Aug 2020

During the COVID pandemic, I worked remotely in the Advanced Silicon Packaging team at GlobalFoundries on the following -

Projects:

An aperture coupled antenna design for 5G Antenna-in-Package system operating at 28 GHz on ANSYS HFSS. The design of the slot/aperture was crucial along with the placement of the ground plane under the radiating patch. The build also involved multi-parameter optimization to minimize return loss (< -20 db) and achieve a gain (?).
Electrical characterization of Deep Trench Capacitors used to decouple the power supply in the 32 nm node on KLayout and ANSYS Q3D. An RLC model was extracted and compared to back-of-envelope calculations as a preliminary check. GF’s integration team would later used this model to evaluate their process understanding and performance objectives.
AC/DC resistance evaluation of a test chip designed to study package-chip interactions on ANSYS Q3D. A via-chain structure was designed and simulated to act as a point-of-reference for studying process maturity.
Characterization of insertion loss induced by a 100 micron Through-Silicon-Via in a test vehicle for 2.5 D/psuedo 3D packaging on ANSYS HFSS and KLayout. Once again, this modeling efforts were aimed to give an initial estimate to the integration team about the performance of their new packaging technology.

Skills: Antenna Design, EM simulations, Silicon modeling

is it fresh GmbH

Antenna Design Intern | Aachen, Germany | May 2018 - Jul 2018 and Jan 2019 - May 2019

is it fresh GmbH works on smart tags that monitor food freshness through humidity and oxygen-levels which are read out using a NFC interface.

I worked two stints in Germany - first, on a DAAD-UGC Scholarship in the summer after my junior year undergrad, and second, as an intern sponsored by the company to pursue my Bachelor’s thesis with them.

Work in a startup is always fun and dynamic. I was involved in many roles - from building SMD prototypes, integrating the printed sensors with NFC circuitry, woodwork and glass cutting for building our own assembly line demo. This place solidified my passion in engineering and helped me decide my path ahead.